1 memory all data sheets are subject to change without notice (858) 503-3300 - fax: (858) 503-3301 - www.maxwell.com cmos logic hex 54hc4050 ?2001 maxwell technologies. all rights reserved. non-inverting buffers 12.19.01 rev 1 1000587 f eatures : ? high speed cmos logic hex non-inverting buffers ?r ad -p ak ? radiation hardened agains t natural space radia- tion ? single event effects: - sel: > 120 mev/mg/cm2 ? total dose hardness: ? - > 100 krad (si), depending upon space mission ? package: -16 pin r ad -p ak ? flat pack ? typical propagation delay: - 6ns at v cc = 5v, c l = 15pf, t a = 25c ? high-to-low voltage level converter for up to v i = 16v ? fanout (over temperature range) -10 lsttl loads (standard outputs) -15 lsttl loads (bus driver outputs) ? balanced propagation delay and transition times ? significant power reduction compared to lsttl logic ics ? 2v to 6v operation ? high noise immunity ?-n il = 30%, n ih = 30% of v cc at v cc = 5v d escription : maxwell technologies' 54hc4050 high speed cmos logic hex non-inverting buffers features a greater than 100 krad(si) total dose tolerance, depending upon space mission. these parts have a modified input pr otection structure that enables them to be used as logic level translators which will convert high-level logic to a low-level logic while operating off the low- level logic supply. for example, 15v input pulse levels can be down-converted to 0v to 5v logic levels. the modified input protection structure protects the input from negative electro- static discharge. the 54hc4050 can be used as simple buff- ers or inverters without level translation. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s. logic diagram
memory 2 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 t able 1. 54hc4050 p inout d escriptions p in s ymbol d escription 1v cc power supply 8v ss ground 13, 16 nc not connected 3, 5, 7, 9, 11, 14 a - f inputs 2 g = a buffered output 4 h = b buffered output 6 i = c buffered output 10 j = d buffered output 12 k = e buffered output 15 l = f buffered output t able 2. 54hc4050 a bsolute m aximum r atings p arameter s ymbol m in m ax u nit storage temperature t s -65 150 c operating temperature range t a -55 125 c dc supply voltage v cc -0.5 7.0 v dc input diode current for v i < -0.5v or v i > v cc +0.5v i ik -20 +20 ma dc output diode current for v o < -0.5v or v o > v cc +0.5v i ok -20 +20 ma dc output source or sink current per output pin for v o > -0.5v or v o < v cc +0.5v i o -25 +25 ma dc v cc or ground current i cc or i gnd -50 +50 ma t able 3. d elta l imits p arameter v ariation i cc 10% of specified value in table 5
memory 3 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 t able 4. 54hc4050 r ecommended o perating c onditions p arameter s ymbol m in m ax u nit supply voltage v cc 26v dc input or output voltage v i , v o 0v cc v input rise and fall time 2v 4.5v 6v -- 1000 500 400 ns temperature range t a -55 125 c t able 5. 54hc4050 dc e lectrical c haracteristics (v cc = 5v 10%, t a = -55 to 125c, unless otherwise specified ) p arameter s ymbol t est c onditions m in m ax u nit high level output voltage cmos loads v oh v i = v ih or v il , i o = -0.02ma v cc = 2v v cc = 4.5v v cc = 6v 1.9 4.4 5.9 -- -- -- v high level output voltage ttl loads v i = v ih or v il , i o = -4ma v cc = 4.5v +25c 3.98 -- -55 to 125c 3.7 v i = v ih or v il , i o = -5.2ma v cc = 6v +25c 5.48 -- -55 to 125c 5.2 -- low level output voltage cmos loads v ol v i = v ih or v il , i o = -0.02ma v cc = 2v v cc = 4.5v v cc = 6v 0.1 0.1 0.1 v low level output voltage ttl loads v i = v ih or v il , i o = 4ma v cc = 4.5v +25c 0.26 -- -55 to 125c 0.4 -- v i = v ih or v il , i o = 5.2ma v cc = 6v +25c 0.36 -- -55 to 125c 0.4 -- high level input voltage v ih v cc = 2v v cc = 4.5v v cc = 6v 1.5 3.15 4.2 -- -- -- v low level input voltage v il v cc = 2v v cc = 4.5v v cc = 6v -- -- -- 0.5 1.35 1.8 v input leakage current i i v cc = 6v, v i = v cc or gnd +25c -- 0.1 a -55 to 125c -- 1 v cc = 6v, v i = 15v +25c -- 0.5 -55 to 125c -- 5
memory 4 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 quiescent device current i cc v i = v cc or gnd, i o = 0ma v cc = 6v +25c -- 2 a -55 to 125c -- 40 t able 6. 54hc4050 ac e lectrical c haracteristics (v cc = 5v 10%, t a = -55 to 125c, unless otherwise specified ) p arameter s ymbol t est c ondition m in m ax u nit propogation delay na to ny t plh, t phl c l = 50pf v cc = 2v +25c -- 85 ns -55 to 125c -- 130 v cc = 4.5v +25c -- 17 -55 to 125c -- 26 v cc = 6v +25c -- 14 -55 to 125c -- 22 transition times (figure 1) t tlh, t thl c l = 50pf v cc = 2v +25c -- 75 ns -55 to 125c -- 110 v cc = 4.5v +25c -- 15 -55 to 125c -- 22 v cc = 6v +25c -- 13 -55 to 125c -- 19 t able 7. 54hc4050 c apacitance 1 1. guaranteed by design. p arameter s ymbol t est c onditions m ax u nit input capacitance c i 10 pf power dissipation capacitance 2, 3 2. c pd is used to determine the dynamic power consumption, per gate. 3. p d = v cc 2 fi (c pd + c l ) where fi = input frequency, c l = output load capacitance, v cc = supply voltage. c pd v cc = 5v 35 pf t able 5. 54hc4050 dc e lectrical c haracteristics (v cc = 5v 10%, t a = -55 to 125c, unless otherwise specified ) p arameter s ymbol t est c onditions m in m ax u nit
memory 5 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 f igure 1. t ransition t imes and p ropogation d elay t imes , c ombination l ogic
memory 6 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 f16-01 note: all dimensions in inches 16-p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.115 0.135 0.150 b 0.015 0.017 0.019 c 0.004 0.005 0.007 d 0.407 0.415 0.423 e 0.275 0.280 0.285 e1 -- -- 0.500 e2 0.150 0.156 0.162 e3 0.030 0.062 -- e 0.050 bsc l 0.325 0.335 0.345 q 0.020 0.033 0.045 s1 0.005 0.024 0.045 n16
memory 7 all data sheets are subject to change without notice ?2001 maxwell technologies. all rights reserved. cmos logic hex non-inverting buffers 54hc4050 12.19.01 rev 1 1000587 important notice: these data sheets are created using the chip manufacturer?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
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